GS816018C中文資料GSI數(shù)據(jù)手冊(cè)PDF規(guī)格書

Functional Description

Applications

The GS816018/36CT is an 18,874,368-bit (16,777,216-bit for x32 version) high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support.

Features

? FT pin for user-configurable flow through or pipeline operation

? Single Cycle Deselect (SCD) operation

? 2.5 V or 3.3 V +10/–10 core power supply

? 2.5 V or 3.3 V I/O supply

? LBO pin for Linear or Interleaved Burst mode

? Internal input resistors on mode pins allow floating mode pins

? Default to Interleaved Pipeline mode

? Byte Write (BW) and/or Global Write (GW) operation

? Internal self-timed write cycle

? Automatic power-down for portable applications

? JEDEC-standard 100-lead TQFP package

? Pb-Free 100-lead TQFP package available