GS816218B中文資料GSI數(shù)據(jù)手冊PDF規(guī)格書

Functional Description

Applications

The GS816218(B/D)/GS816236(B/D)/GS816272(C) is an 18,874,368-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support.

Features

? FT pin for user-configurable flow through or pipeline operation

? Single/Dual Cycle Deselect selectable

? IEEE 1149.1 JTAG-compatible Boundary Scan

? ZQ mode pin for user-selectable high/low output drive

? 2.5 V or 3.3 V +10/–10 core power supply

? LBO pin for Linear or Interleaved Burst mode

? Internal input resistors on mode pins allow floating mode pins

? Default to SCD x18/x36 Interleaved Pipeline mode

? Byte Write (BW) and/or Global Write (GW) operation

? Internal self-timed write cycle

? Automatic power-down for portable applications

? JEDEC-standard 119-, 165-, and 209-bump BGA package