GS8170DW36C中文資料GSI數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

SigmaRAM Family Overview

GS8170DW36/72 SigmaRAMs are built in compliance with the SigmaRAM pinout standard for synchronous SRAMs. They are 18,874,368-bit (18Mb) SRAMs. This family of wide, very low voltage CMOS I/O SRAMs is designed to operate at the speeds needed to implement economical high performance networking systems.

Features

? Double Late Write mode, Pipelined Read mode

? JEDEC-standard SigmaRAM? pinout and package

? 1.8 V +150/–100 mV core power supply

? 1.5 V or 1.8 V CMOS Interface

? ZQ controlled user-selectable output drive strength

? Dual Cycle Deselect

? Burst Read and Write option

? Fully coherent read and write pipelines

? Echo Clock outputs track data output drivers

? Byte write operation (9-bit bytes)

? 2 user-programmable chip enable inputs

? IEEE 1149.1 JTAG-compliant Serial Boundary Scan

? 209-bump, 14 mm x 22 mm, 1 mm bump pitch BGA package

? Pin-compatible with future 36Mb, 72Mb, and 144Mb devices