GS8180Q36D-100中文資料GSI數(shù)據(jù)手冊PDF規(guī)格書

SigmaRAM? Family Overview

GS8180Q18 are built in compliance with the SigmaQuad SRAM pinout standard for Separate I/O synchronous SRAMs. They are 18,874,368-bit (18Mb) SRAMs. These are the first in a family of wide, very low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems.

SigmaQuad SRAMs are offered in a number of configurations. Some emulate and enhance other synchronous separate I/O SRAMs. A higher performance SDR (Single Data Rate) Burst of 2 version is also offered. The logical differences between the protocols employed by these RAMs hinge mainly on various combinations of address bursting, output data registering, and write cueing. Along with the Common I/O family of SigmaRAMs, the SigmaQuad family of SRAMs allows a user to implement the interface protocol best suited to the task at hand.

Features

? Simultaneous Read and Write SigmaQuad? Interface

? JEDEC-standard pinout and package

? Dual Double Data Rate interface

? Byte Write controls sampled at data-in time

? Burst of 2 Read and Write

? 1.8 V +150/–100 mV core power supply

? 1.5 V or 1.8 V HSTL Interface

? Pipelined read operation

? Fully coherent read and write pipelines

? ZQ mode pin for programmable output drive strength

? IEEE 1149.1 JTAG-compliant Boundary Scan

? 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package

? Pin-compatible with future 36Mb, 72Mb, and 144Mb devices