GS82032AT-100中文資料GSI數(shù)據(jù)手冊PDF規(guī)格書

Features

? FT pin for user-configurable flow through or pipelined operation

? Single Cycle Deselect (SCD) operation

? 3.3 V +10/–5 core power supply

? 2.5 V or 3.3 V I/O supply

? LBO pin for Linear or Interleaved Burst mode

? Internal input resistors on mode pins allow floating mode pins

? Default to Interleaved Pipelined mode

? Byte Write (BW) and/or Global Write (GW) operation

? Common data inputs and data outputs

? Clock Control, registered, address, data, and control

? Internal self-timed write cycle

? Automatic power-down for portable applications

? JEDEC standard 100-lead TQFP package

? Pb-Free 100-lead TQFP package available

Applications

The GS82032A is a 2,097,152-bit high performance

synchronous SRAM with a 2-bit burst address counter.

Although of a type originally developed for Level 2 Cache

applications supporting high performance CPUs, the device

now finds application in synchronous SRAM applications,

ranging from DSP main store to networking chip set support.