GS82564Z36GD-333V中文資料GSI數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

Functional Description

The GS82564Z18/36-xxxV is a 288Mbit Synchronous Static SRAM. GSIs NBT SRAMs, like ZBT, NtRAM, NoBL or other pipelined read/double late write or flow through read/single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles.

Features

? NBT (No Bus Turn Around) functionality allows zero wait

Read-Write-Read bus utilization; fully pin-compatible with

both pipelined and flow through NtRAM?, NoBL? and

ZBT? SRAMs

? 1.8 V or 2.5 V +10/–10 core power supply

? 1.8 V or 2.5 V I/O supply

? User-configurable Pipeline and Flow Through mode

? ZQ mode pin for user-selectable high/low output drive

? IEEE 1149.1 JTAG-compatible Boundary Scan

? LBO pin for Linear or Interleave Burst mode

? Pin-compatible with 4Mb, 9Mb, 18Mb, 36Mb, and 72Mb

devices

? Byte write operation (9-bit Bytes)

? 3 chip enable signals for easy depth expansion

? ZZ Pin for automatic power-down

? RoHS-compliant 119- and 165-bump BGA packages