Features
? Aerospace-Level Product
? 2.0 clock Latency with DLL on
? 1.0 clock Latency with DLL off
? Optional DLL-controlled output timing
? Can be operated with DLL on or off
? Simultaneous Read and Write SigmaQuad? Interface
? JEDEC-standard pinout and package
? Dual Double Data Rate interface
? Byte Write controls sampled at data-in time
? Burst of 4 Read and Write
? Dual-Range On-Die Termination (ODT) on Data (D), Byte
Write (BW), and Clock (K, K) inputs
? 1.8 V +100/–100 mV core power supply
? 1.5 V or 1.8 V HSTL Interface
? Pipelined read operation
? Fully coherent read and write pipelines
? ZQ pin for programmable output drive strength
? Data Valid Pin (QVLD) Support
? IEEE 1149.1 JTAG-compliant Boundary Scan
? 165-bump Ceramic Column Grid Array (CCGA) and
165-bump Land Grid Array (LGA) packages
Radiation Performance
? Total Ionizing Dose (TID) > 100krads(Si)
? Single Event Latchup Immunity > 77.3 MeV.cm2
/mg (125?C)
SigmaQuad? Family Overview
The GS82612DT19/37, GS81332DT19/37, and
GS8692DT19/37 are built in compliance with the SigmaQuadII+ SRAM pinout standard for Separate I/O synchronous
SRAMs. They are 301,989,888-bit (288Mb), 150,994,944-bit
(144Mb), and 75,497,472-bit (72Mb) SRAMs. These
SigmaQuad SRAMs are just one element in a family of low
power, low voltage HSTL I/O SRAMs designed to operate at
the speeds needed to implement economical high performance
networking systems.
Clocking and Addressing Schemes
The Rad-Hard SigmaQuad-II+ SRAMs are synchronous
devices. They employ two input register clock inputs, K and K.
K and K are independent single-ended clock inputs, not
differential inputs to a single differential clock input buffer.
Each internal read and write operation in a SigmaQuad-II+ B4
RAM is four times wider than the device I/O bus. An input
data bus de-multiplexer is used to accumulate incoming data
before it is simultaneously written to the memory array. An
output data multiplexer is used to capture the data produced
from a single memory array read and then route it to the
appropriate output drivers as needed. Therefore, the address
field of a SigmaQuad-II+ B4 RAM is always two address pins
less than the advertised index depth (e.g., the 16M x 18 has a
4M addressable index).
