GS84118B-133中文資料GSI數據手冊PDF規(guī)格書

Functional Description

The GS84118 is a 256K x 18 high performance synchronous SRAM with integrated Tag RAM comparator. A 2-bit burst counter is included to provide burst interface with PentiumTM and other high performance CPUs.

Features

? 3.3 V +10/–5 core power supply, 2.5 V or 3.3 V I/O supply

? Intergrated data comparator for Tag RAM application

? FT mode pin for flow through or pipeline operation

? LBO pin for Linear or Interleave (PentiumTM and X86) Burst mode

? Synchronous address, data I/O, and control inputs

? Synchronous Data Enable (DE)

? Asynchronous Output Enable (OE)

? Asynchronous Match Output Enable (MOE)

? Byte Write (BWE) and Global Write (GW) operation

? Three chip enable signals for easy depth expansion

? Internal self-timed write cycle

? JTAG Test mode conforms to IEEE standard 1149.1

? JEDEC-standard 100-lead TQFP package and 119-BGA: T:TQFP or B: BGA