GS881E36T-100中文資料GSI數(shù)據(jù)手冊(cè)PDF規(guī)格書

Functional Description

Applications

The GS881E18//36T is a 9,437,184-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support.

1.10 9/2000Features

? FT pin for user-configurable flow through or pipelined

operation

? Dual Cycle Deselect (DCD) operation

? IEEE 1149.1 JTAG-compatible Boundary Scan

? On-chip write parity checking; even or odd selectable

? 3.3 V +10/–5 core power supply

? 2.5 V or 3.3 V I/O supply

? LBO pin for Linear or Interleaved Burst mode

? Internal input resistors on mode pins allow floating mode pins

? Default to Interleaved Pipeline mode

? Byte Write (BW) and/or Global Write (GW) operation

? Common data inputs and data outputs

? Clock Control, registered, address, data, and control

? Internal self-timed write cycle

? Automatic power-down for portable applications

? 100-lead TQFP package