GS9035CCPJ中文資料根努姆數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

DESCRIPTION

The GS9035C is a high performance clock and data recovery IC designed for serial digital data. The GS9035C receives either single-ended or differential PECL data and outputs differential PECL clock and retimed data signals.

FEATURES

? adjustment-free operation

? auto-rate selection for 4 SMPTE data rates: 143, 177, 270, 360Mb/s

? data rate indication output

? serial data output mute when PLL is not locked

? operation independent of SAV/EAV sync signals

? low jitter, low power

? single external VCO resistor for operation with four input data rates

? large input jitter tolerance: typically 0.50 UI beyond loop bandwidth at 270Mb/s

? power savings mode (output serial clock disable)

? system friendly: serial clock remains active when data outputs muted

? robust lock detect

APPLICATIONS

The GS9035C is used for Clock and Data recovery, and Jitter elimination for all high speed serial digital interface applications involving SMPTE 259M and other data standards.