GTLP10B320集成電路（IC）的通用總線功能規(guī)格書PDF中文資料

General Description

The GTLP10B320 is a 10-bit Universal bus driver and receiver, with separate LVTTL inputs and outputs and a feedback path for diagnostics, that provides LVTTL to GTLP signal level translation. High speed backplane operation is a direct result of GTLP’s reduced output swing (

Features

■ Bidirectional interface between GTLP and LVTTL logic levels

■ Variable edge rate control pin to select desired edge rate on GTLP port (VERC)

■ VREF pin provides external supply reference voltage for receiver threshold adjustibility

■ Split LVTTL inputs and outputs

■ Special PVT compensation circuitry to provide consistent performance over variations of process, supply voltage and temperature

■ A feedback path for control and diagnostics monitoring

■ TTL compatible driver and control inputs

■ Designed using Fairchild advanced BiCMOS technology

■ Bushold data inputs on A port to eliminate the need for external pull-up resistors for unused inputs

■ Power up/down and power off high impedance for liveinsertion

■ Open drain on GTLP to support wired-or connection

■ Flow through pinout optimizes PCB layout

■ A Port source/sink ?24mA/+24mA

■ B Port sink +50mA