HB54A5129F1U-10B中文資料美光科技數(shù)據(jù)手冊PDF規(guī)格書

Description

The HB54A5129F1U is a 64M × 72 × 1 bank Double Data Rate (DDR) SDRAM Module, mounted 18 pieces of 256Mbits DDR SDRAM (HM5425401BTT) sealed in TSOP package, 1 piece of PLL clock driver, 2 pieces of register driver and 1 piece of serial EEPROM (2k bits EEPROM) for Presence Detect (PD). Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data transfer is realized by the 2-bit prefetch-pipelined architecture.

Features

? 184-pin socket type package (dual lead out)

- Outline: 133.35mm (Length) × 30.48mm (Height) × 4.00mm (Thickness)

- Lead pitch: 1.27mm

? 2.5V power supply (VCC/VCCQ)

? SSTL-2 interface for all inputs and outputs

? Clock frequency: 143MHz/133MHz/125MHz (max.)

? Data inputs and outputs are synchronized with DQS

? 4 banks can operate simultaneously and independently (Component)

? Burst read/write operation

? Programmable burst length: 2, 4, 8

- Burst read stop capability

? Programmable burst sequence

- Sequential

- Interleave

? Start addressing capability

- Even and Odd

? Programmable /CAS latency (CL): 3, 3.5

? 8192 refresh cycles: 7.8μs (8192/64ms)

? 2 variations of refresh

- Auto refresh

- Self refresh