HC805K3GRS/D中文資料恩智浦?jǐn)?shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

Features

? Low-Cost HC05 Core

? 16-Pin PDIP or SOIC Package

? 928 Bytes of User EEPROM (Including Eight Bytes of User

Vectors)

? 64 Bytes of User RAM

? 128 Bits of Personality EEPROM (Not Memory Mapped)

Programmed using User Software or during User EEPROM

Programming

? On-Chip Charge Pump for In-Circuit Programming of the

Personality EEPROM at 3.0 to 5.5 Vdc.

? 8-Bit Free-Running Timer

? 4-Stage Selectable Real-Time Interrupt Generator

? 10 Bidirectional Input/Output (I/O) Lines Including:

– 8 mA Sink Capability on Four I/O Pins (PA7–PA4)

– Mask Option Register Bit for Software Programmable

Pulldowns on All I/O Pins

– Mask Option Register Bit for Port Interrupts on Four I/O Pins

(PA3–PA0) (Keyboard Scan Feature)

? IRQ Interrupt Hardware Mask, Flag Bit, and Request Bit

? Mask Option Register Bit for Sensitivity on IRQ Interrupt (Edgeand

Level-Sensitive or Edge-Sensitive Only)

? On-Chip Oscillator (Mask Option Register Bits for Crystal/Ceramic

Resonator Oscillator with Internal 2 MW Resistor, and 2-Pin or 3-

Pin Resistor Capacitor (RC) Oscillator)

? Mask Option Register Bit for Reduced Startup Delay Time with RC

Oscillator Options

? Mask Option Register Bit for Computer Operating Properly (COP)

Watchdog System

? Power-Saving Stop and Wait Mode Instructions

? Mask Option Register Bit to Convert STOP Instruction to Halt

Mode

? Illegal Address Reset

? Internal Steering Diode and Pullup Resistor on RESET Pin to VDD

? Internal RESET Pin Pulldown from COP Watchdog and ILADR