HCF4060Y集成電路（IC）的計(jì)數(shù)器除法器規(guī)格書PDF中文資料

HCF4060Y屬于集成電路（IC）的計(jì)數(shù)器除法器。由意法半導(dǎo)體集團(tuán)制造生產(chǎn)的HCF4060Y計(jì)數(shù)器，除法器計(jì)數(shù)器和除法器 IC 是數(shù)字邏輯器件，可對(duì)輸入發(fā)生的邏輯轉(zhuǎn)換進(jìn)行計(jì)數(shù)，然后使用多個(gè)并行輸出重新發(fā)送累加的計(jì)數(shù)，和/或生成單個(gè)輸出信號(hào)轉(zhuǎn)換，從而對(duì)應(yīng)用某些整數(shù)數(shù)量輸入信號(hào)轉(zhuǎn)換進(jìn)行響應(yīng)。除了簡單的事件計(jì)數(shù)，它們還可用于各種頻率合成應(yīng)用。

Description

The HCF4060 device is a monolithic integrated circuit fabricated in MOS (metal oxide semiconductor) technology available in SO16 and PDIP16 packages.

The HCF4060 device consists of an oscillator section and 14 ripple carry binary counter stages.

The oscillator configuration allows design of either RC or crystal oscillator circuits. A RESET input is provided which resets the counter to the all 0’s state and disables the oscillator. A high level on the RESET line accomplishes the reset function. All counter stages are master slave flip-flops. The state of the counter is advanced one step in binary order on the negative transition of φ1 (and φ0). All inputs and outputs are fully buffered. Schmitt trigger action on the clock pin permits unlimited clock rise and fall time.

Features

? Medium speed operation

? Common reset

? Fully static operation

? Buffered inputs and outputs

? Quiescent current specified up to 20 V

? 5 V, 10 V and 15 V parametric ratings

? Input leakage current: II = 100 nA (max.)

at VDD = 18 V, TA = 25 °C

? 100 tested for quiescent current

? ESD performance

– HBM: 1 kV

– MM: 200 V

– CDM: 1 kV

Applications

? Automotive

? Industrial

? Computer

? Consumer