HCS190HMSR中文資料Intersil數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

Description

The Intersil HCS190MS is an asynchronously presettable BCD Decade synchronous counter. Presetting the counter to the number on the preset data inputs (P0 - P3) is accomplished by a low on the parallel load input (PL). Counting occurs when (PL) is high, Count Enable (CE) is low and the Up/Down (U/D) input is either low for up-counting or high for down-counting. The counter is incremented or decremented synchronously with the low-to-high transition of the clock.

Features

? 3 Micron Radiation Hardened SOS CMOS

? Total Dose 200K RAD (Si)

? SEP Effective LET No Upsets: >100 MEV-cm2/mg

? Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day (Typ)

? Dose Rate Survivability: >1 x 1012 RAD (Si)/s

? Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse

? Latch-Up Free Under Any Conditions

? Military Temperature Range: -55°C to +125°C

? Significant Power Reduction Compared to LSTTL ICs

? DC Operating Voltage Range: 4.5V to 5.5V

? Input Logic Levels

??? - VIL = 30 of VCC Max

??? - VIH = 70 of VCC Min

? Input Current Levels Ii ≤ 5μA at VOL, VOH