HCTS112DMSR中文資料Intersil數(shù)據(jù)手冊PDF規(guī)格書

Description

The Intersil HCTS112MS is a Radiation Hardened dual JK flip-flop with set and reset. The flip-flop changes states with the negative transition of the clock (CP1N or CP2N).

The HCTS112MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family.

The HCTS112MS is supplied in a 16 lead Ceramic flatpack (K suffix) or a SBDIP Package (D suffix).

Features

? 3 Micron Radiation Hardened SOS CMOS

? Total Dose 200K RAD (Si)

? SEP Effective LET No Upsets: >100 MEV-cm2/mg

? Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day (Typ)

? Dose Rate Survivability: >1 x 1012 RAD (Si)/s

? Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse

? Cosmic Ray Upset Rate 2 x 10-9 Errors/Bit Day (Typ)

? Latch-Up Free Under Any Conditions

? Military Temperature Range: -55°C to +125°C

? Significant Power Reduction Compared to LSTTL ICs

? DC Operating Voltage Range: 4.5V to 5.5V

? LSTTL Input Compatibility

??? - VIL = 0.8V Max

??? - VIH = VCC/2 Min

? Input Current Levels Ii ≤ 5μA at VOL, VOH