HCTS160DMSR中文資料Intersil數(shù)據(jù)手冊PDF規(guī)格書

Description

The Intersil HCTS160MS is a Radiation Hardened high speed

presettable BCD decade synchronous counter that features an

asynchronous reset and look-ahead carry logic. Counting and

parallel presetting are accomplished synchronously with the lowto-high transition of the clock. A low level on the synchronous

parallel enable input, SPE, disables counting and allows data at

the preset inputs, P0 - P3, to be loaded into the counter. The

counter is reset by a low on the master reset input, MR. Two count

enables, PE and TE are provided for n-bit cascading. TE also

controls the terminal count output, TC. The terminal count output

indicates a maximum count for one clock pulse and is used to

enable the next cascaded stage to count.

The HCTS160MS utilizes advanced CMOS/SOS technology to

achieve high-speed operation. This device is a member of

radiation hardened, high-speed, CMOS/SOS Logic Family.

The HCTS160MS is supplied in a 16 lead Ceramic flatpack

(K suffix) or a SBDIP Package (D suffix).

Features

? 3 Micron Radiation Hardened SOS CMOS

? Total Dose 200K RAD (Si)

? SEP Effective LET No Upsets: >100 MEV-cm2/mg

? Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day

(Typ)

? Dose Rate Survivability: >1 x 1012 RAD (Si)/s

? Dose Rate Upset: >1010 RAD (Si)/s 20ns Pulse

? Latch-Up Free Under Any Conditions

? Fanout (Over Temperature Range)

-Standard Outputs 10 LSTTL Loads

? Military Temperature Range: -55oC to +125oC

? Significant Power Reduction Compared to LSTTL ICs

? DC Operating Voltage Range: 4.5V to 5.5V

? LSTTL Input Compatibility

-VIL = 0.8V Max

-VIH = VCC/2 Min

? Input Current Levels Ii ≤ 5μA @ VOL, VOH