HCTS191DMSR中文資料Intersil數(shù)據(jù)手冊(cè)PDF規(guī)格書

Description

The Intersil HCTS191MS is a Radiation Hardened asynchronously presettable 4 bit binary up/down synchronous counter.

Presetting the counter to the number on the preset data inputs

(P0 - P3) is accomplished by a low asynchronous parallel load

input (PL). Counting occurs when PL is high, Count Enable (CE)

is low, and the Up/Down (U/D) input is either low for up-counting

or high for down-counting. The counter is incremented or decremented synchronously with the low-to-high transition of the clock.

When an overflow or underflow of the counter occurs, the

Terminal Count output (TC), which is low during counting, goes

high and remains high for one clock cycle. This output can be

used for look-ahead carry in high speed cascading. The TC

output also initiates the Ripple Clock output (RC) which, normally

high, goes low and remains low for the low-level portion of the

clock pulse. These counter can be cascaded using the Ripple

Carry output.

The HCTS191MS utilizes advanced CMOS/SOS technology to

achieve high-speed operation. This device is a member of

radiation hardened, high-speed, CMOS/SOS Logic Family.

The HCTS191MS is supplied in a 16 lead Ce

Features

? 3 Micron Radiation Hardened CMOS SOS

? Total Dose 200K RAD (Si)

? SEP Effective LET No Upsets: >100 MEV-cm2/mg

? Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/BitDay (Typ)

? Dose Rate Survivability: >1 x 1012 RAD (Si)/s

? Dose Rate Upset: >1010 RAD (Si)/s 20ns Pulse

? Cosmic Ray Upset Immunity 2 x 10-9 Errors/Bit Day

? Latch-Up Free Under Any Conditions

? Fanout (Over Temperature Range)

- Standard Outputs - 10 LSTTL Loads

? Military Temperature Range: -55oC to +125oC

? Significant Power Reduction Compared to LSTTL ICs

? DC Operating Voltage Range: 4.5V to 5.5V

? LSTTL Input Compatibility

- VIL = 0.8V Max

- VIH = VCC/2 Min

? Input Current Levels Ii ≤ 5μA @ VOL, VOH