HD74HCT137中文資料日立數(shù)據手冊PDF規(guī)格書

Description

The HD74HCT137 implements a three-to-eight line decoder with latches on the three address inputs. When GL goes from low to high, the address present at the select inputs (A, B and C) is stored in the latches. As long as GL remains high no address changes will be recognized. Output enable controls, G1 and G2, control the state of the outputs independently of the select or latch-enable inputs.

Features

? LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility

? High Speed Operation: tpd (A, B, C to Y) = 18 ns typ (CL = 50 pF)

? High Output Current: Fanout of 10 LSTTL Loads

? Wide Operating Voltage: VCC = 4.5 to 5.5 V

? Low Input Current: 1 μA max

? Low Quiescent Supply Current: ICC (static) = 4 μA max (Ta = 25°C)