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HD74LS42RPEL中文資料瑞薩數(shù)據(jù)手冊PDF規(guī)格書
HD74LS42RPEL規(guī)格書詳情
This monolithic decimal decoder consists of eight inverters and ten four-input NAND gates. The inverters are connected in pairs to make BCD input data available for decoding by NAND gates. Full decoding of valid input logic ensures that all outputs remain off for all invalid input conditions.
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23+ |
NA/ |
2633 |
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92+ |
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4600 |
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RENESAS |
24+ |
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65300 |
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24+ |
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30617 |
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HITACHI/日立 |
23+ |
DIP |
90000 |
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12+14+ |
NA |
880000 |
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1948+ |
DIP |
6852 |
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DIP |
68900 |
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05+ |
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176 |
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