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HD74LV374AFPEL中文資料瑞薩數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

HD74LV374AFPEL
廠商型號(hào)

HD74LV374AFPEL

功能描述

Octal Edge-Triggered D-type Flip-Flops with 3-state Outputs

文件大小

83.6 Kbytes

頁(yè)面數(shù)量

10 頁(yè)

生產(chǎn)廠商 Renesas Technology Corp
企業(yè)簡(jiǎn)稱

RENESAS瑞薩

中文名稱

瑞薩科技有限公司官網(wǎng)

原廠標(biāo)識(shí)
數(shù)據(jù)手冊(cè)

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更新時(shí)間

2025-1-18 23:00:00

HD74LV374AFPEL規(guī)格書(shū)詳情

Description

The HD74LV374A has eight edge trigger D type flip flops with three state outputs in a 20 pin package. Data at the D inputs meeting set up requirements, are transferred to the Q outputs on positive going transitions of the clock input. When the clock input goes low, data at the D inputs will be retained at the outputs until clock input returns high again. When a high logic level is applied to the output control input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements. Low-voltage and high-speed operation is suitable for the battery-powered products (e.g., notebook computers), and the low-power consumption extends the battery life.

Features

? VCC = 2.0 V to 5.5 V operation

? All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)

? All outputs VO (Max.) = 5.5 V (@VCC = 0 V)

? Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)

? Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25°C)

? Output current ±8 mA (@VCC = 3.0 V to 3.6 V), ±16 mA (@VCC = 4.5 V to 5.5 V)

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23+
NA/
4000
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HIT
23+
SOP
20000
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RENESAS
2020+
TSSOP
80000
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2006
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4000
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RENESAS
21+
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4000
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HD
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35200
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RENESAS
23+
NA
2481
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RENESAS
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New
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68900
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