HEF40163中文資料飛利浦?jǐn)?shù)據(jù)手冊(cè)PDF規(guī)格書

DESCRIPTION

The HEF40163B is a fully synchronous edge-triggered 4-bit binary counter with a clock input (CP), four synchronous parallel data inputs (P0 to P3), four synchronous mode control inputs (parallel enable (PE), count enable parallel (CEP), count enable trickle (CET) and synchronous reset (SR)), buffered outputs from all four bit positions (O0 to O3) and a terminal count output (TC).

Operation is fully synchronous and occurs on the LOW to HIGH transition of CP. When PE is LOW, the next LOW to HIGH transition of CP loads data into the counter from P0 to P3. When PE is HIGH, the next LOW to HIGH transition of CP advances the counter to its next state only if both CEP and CET are HIGH; otherwise no change occurs in the state of the counter. TC is HIGH when the state of the counter is 15 (O0 to O3 = HIGH) and when CET is HIGH. A LOW on SR sets all outputs (O0 to O3 and TC) LOW on the next LOW to HIGH transition of CP, independent of the state of all other synchronous mode control inputs (CEP, CET and PE). Multistage synchronous counting is possible without additional components by using a carry look-ahead counting technique; in this case, TC is used to enable successive cascaded stages. CEP, CET, PE and SR must be stable only during the set-up time before the LOW to HIGH transition of CP.