HEF4021B集成電路（IC）的移位寄存器規(guī)格書PDF中文資料

1. General description

The HEF4021B is an 8-bit static shift register (parallel-to-serial converter) with a synchronous

serial data input (DS), a clock input (CP), an asynchronous active HIGH parallel load input (PL),

eight asynchronous parallel data inputs (D0 to D7) and buffered parallel outputs from the last three

stages (Q5 to Q7). Each register stage is a D-type master-slave flip-flop with a set direct (SD) and

clear direct (CD) input. Information on D0 to D7 is asynchronously loaded into the register while PL

is HIGH, independent of CP and DS. When PL is LOW, data on DS is shifted into the first register

position and all the data in the register is shifted one position to the right on the LOW-to-HIGH

transition of CP. Schmitt trigger action makes the clock input highly tolerant of slower rise and fall

times.

The device operates over a recommended VDD power supply range of 3 V to 15 V referenced to

VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input.

2. Features and benefits

? Wide supply voltage range from 3.0 V to 15.0 V

? CMOS low power dissipation

? High noise immunity

? Tolerant of slower rise and fall times

? Fully static operation

? 5 V, 10 V, and 15 V parametric ratings

? Standardized symmetrical output characteristics

? Complies with JEDEC standard JESD 13-B

? ESD protection:

? HBM JESD22-A114F exceeds 2000 V

? MM JESD22-A115-B exceeds 200 V

? Specified from -40 °C to +85 °C and from -40 °C to +125 °C