HEF4040BT-Q100集成電路（IC）的計(jì)數(shù)器除法器規(guī)格書PDF中文資料

1. General description

The HEF4040B is a 12-stage binary ripple counter with a clock input (CP), an overriding

asynchronous master reset input (MR) and twelve fully buffered outputs (Q0 to Q11). The counter

advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages and

forces all outputs LOW, independent of CP. Each counter stage is a static toggle flip-flop. Inputs

are overvoltage tolerant to 15 V. This enables the device to be used in HIGH-to-LOW level shifting

applications.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100

(Grade 3) and is suitable for use in automotive applications.

2. Features and benefits

? Automotive product qualification in accordance with AEC-Q100 (Grade 3)

? Specified from -40 °C to +85 °C

? Wide supply voltage range from 3.0 V to 15.0 V

? CMOS low power dissipation

? High noise immunity

? Tolerant of slow clock rise and fall time

? Fully static operation

? 5 V, 10 V, and 15 V parametric ratings

? Standardized symmetrical output characteristics

? Complies with JEDEC standard JESD 13-B

? ESD protection:

? HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

? CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

3. Applications

? Frequency dividing circuits

? Time delay circuits

? Control counters