HEF4517B_09中文資料恩智浦數(shù)據(jù)手冊PDF規(guī)格書

General description

The HEF4517B consists of two identical, independent 64-bit static shift registers. Each register has separate clock (nCP), data input (nD), parallel input-enable/output-enable (nPE/OE) and four 3-state outputs of the 16th, 32nd, 48th, and 64th bit positions (nQ16 to nQ64). Data at the nD input is entered into the first bit on the LOW-to-HIGH transition of the clock, regardless of the state of nPE/OE.

When nPE/OE is LOW, the outputs are enabled and it is in the 64-bit serial mode.

Features

■ Tolerant of slow clock rise and fall times

■ Fully static operation

■ 5 V, 10 V, and 15 V parametric ratings

■ Standardized symmetrical output characteristics

■ Operates across the full industrial temperature range ?40 °C to +85 °C

■ Complies with JEDEC standard JESD 13-B

Applications

■ Industrial