HM1-6561SLASH883中文資料Intersil數(shù)據(jù)手冊PDF規(guī)格書

Description

The HM-6561/883 is a 256 x 4 static CMOS RAM fabricated using self-aligned silicon gate technology. Synchronous circuit design techniques are employed to achieve high performance and low power operation.

Features

? This Circuit is Processed in Accordance to MIL-STD-883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1.

? Low Power Standby . . . . . . . . . . . . . . . . . . . . 50μW Max

? Low Power Operation . . . . . . . . . . . . . 20mW/MHz Max

? Fast Access Time. . . . . . . . . . . . . . . . . . . . . . 200ns Max

? Data Retention . . . . . . . . . . . . . . . . . . . . . . . .at 2.0V Min

? TTL Compatible Input/Output

? High Output Drive - 1 TTL Load

? On-Chip Address Registers

? Common Data In/Out

? Three-State Output

? Easy Microprocessor Interfacing