HM64YLB36512中文資料瑞薩數(shù)據(jù)手冊(cè)PDF規(guī)格書

Description

The HM64YLB36512 is a synchronous fast static RAM organized as 512-kword × 36-bit. It has realized high speed access time by employing the most advanced CMOS process and high speed circuit designing technology. It is most appropriate for the application which requires high speed, high density memory and wide bit width configuration, such as cache and buffer memory in system. It is packaged in standard 119-bump BGA.

Features

? 2.5 V ± 5 operation and 1.5 V (VDDQ)

? 16M bit density

? Byte write control (4 byte write selects, one for each 9-bit)

? Optional ×18 configuration

? HSTL compatible I/O

? Programmable impedance output drivers

? Asynchronous G output control

? Asynchronous sleep mode

? FC-BGA 119pin package with SRAM JEDEC standard pinout

? Limited set of boundary scan JTAG IEEE 1149.1 compatible

? Mode selectable among late write, associative late write (late select) and register-latch

? Late select mode:

- Synchronous register to register operation

- Late SAS select, selects which half of 72-bit core data to return on reads

- SAS serves as way select

- Differential HSTL clock inputs

? Late write mode:

- Synchronous register to register operation

- Differential HSTL clock inputs

? Register-latch mode:

- Synchronous register to latch operation

- Differential pseudo-HSTL clock inputs