HMN28D-70I中文資料HANBIT數(shù)據(jù)手冊PDF規(guī)格書

GENERAL DESCRIPTION

The HMN28D are 16,384-bit, fully static, nonvolatile SRAM’s organized as 2,048 bytes by 8 bits. Each NVSRAM has a self-contained lithium energy source and control circuitry, which constantly monitors Vcc for an out-of-tolerance condition. When such a condition occurs, the lithium energy source is automatically switched on and writes protection is unconditionally enabled to prevent data corruption. The HMN28D devices can be used in place of existing 2K x 8 SRAM’s directly conforming to the popular byte wide 24-pin DIP standard. There is no limit on the number of write cycles that can be executed and no additional support circuitry is required for microprocessor interfacing.

The HMN28D uses extremely low standby current CMOS SRAM’s, coupled with small lithium coin cells to provide nonvolatility without long write-cycle times and the write-cycle limitations associated with EEPROM.

FEATURES

? Access time : 70, 85, 120 and 150ns

? High-density design : 2KByte Design

? Battery internally isolated until power is applied

? JEDEC standard 24-pin DIP Package

? Low-power CMOS

? Unlimited writes cycles

? Data retention in the absence of VCC

? 10-years minimum data retention in absence of power

? Automatic write-protection during power-up/power-down cycles

? Data is automatically protected during power loss

? Conventional SRAM operation; unlimited write cycles