HMT112R7AFP8C中文資料海力士數(shù)據(jù)手冊(cè)PDF規(guī)格書

Description

This Hynix DDR3 SDRAM Registered Dual In-Line Memory Module (DIMM) series consists of 1Gb A generation. These are intended for use as main memory in server and workstation systems, providing a high performance 8 byte interface in 133.35mm width form factor of industry standard. It is suitable for easy interchange and addition.

Features

? VDD=VDDQ=1.5V

? VDDSPD=3.3V to 3.6V

? Fully differential clock inputs (CK, CK) operation

? Differential Data Strobe (DQS, DQS)

? On chip DLL align DQ, DQS and /DQS transition with CK transition

? DM masks write data-in at the both rising and falling edges of the data strobe

? All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock

? Programmable CAS latency 5, 6, 7, 8, 9, 10, and (11) supported

? Programmable additive latency 0, CL-1, and CL-2 sup ported

? Programmable CAS Write latency (CWL) = 5, 6, 7, 8

? Programmable burst length 4/8 with both nibble sequential and interleave mode

? BL switch on the fly

? 8 banks

? 8K refresh cycles /64ms

? DDR3 SDRAM Package: JEDEC standard 78ball FBGA(x4/x8), 96ball FBGA(x16) with support balls

? Driver strength selected by EMRS

? Dynamic On Die Termination supported

? Asynchronous RESET pin supported

? ZQ calibration supported

? TDQS (Termination Data Strobe) supported (x8 device based only)

? Write Levelization supported

? Auto Self Refresh supported

? 8 bit pre-fetch

? Heat Spreader installed for 4GB/8GB

? SPD with Integrated TS of Class B