HS-3282_02中文資料Intersil數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

Description

The HS-3282 is a high performance CMOS bus interface circuit that is intended to meet the requirements of ARINC Specification 429, and similar encoded, time multiplexed serial data protocols. This device is intended to be used with the HS-3182, a monolithic Dl bipolar differential line driver designed to meet the specifications of ARINC 429. The ARINC 429 bus interface circuit consists of two (2) receivers and a transmitter operating independently as shown in Figure 1. The two receivers operate at a frequency that is ten (10) times the receiver data rate, which can be the same or different from the transmitter data rate. Although the two receivers operate at the same frequency, they are functionally independent and each receives serial data asynchronously. The transmitter section of the ARINC bus interface circuit consists mainly of a First-In First-Out (FIFO) memory and timing circuit. The FIFO memory is used to hold up to eight (8) ARINC data words for transmission serially.

Features

? ARlNC Specification 429 Compatible

? Data Rates of 100 Kilobits or 12.5 Kilobits

? Separate Receiver and Transmitter Section

? Dual and Independent Receivers, Connecting Directly to ARINC Bus

? Serial to Parallel Receiver Data Conversion

? Parallel to Serial Transmitter Data Conversion

? Word Lengths of 25 or 32 Bits

? Parity Status of Received Data

? Generate Parity of Transmitter Data

? Automatic Word Gap Timer

? Single 5V Supply

? Low Power Dissipation

? Full Military Temperature Range