首頁(yè)>HS1-3182-8>規(guī)格書(shū)詳情

HS1-3182-8中文資料Intersil數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

HS1-3182-8
廠商型號(hào)

HS1-3182-8

功能描述

ARINC 429 Bus Interface Line Driver Circuit

文件大小

199.6 Kbytes

頁(yè)面數(shù)量

7 頁(yè)

生產(chǎn)廠商 Intersil Corporation
企業(yè)簡(jiǎn)稱

Intersil

中文名稱

Intersil Corporation官網(wǎng)

原廠標(biāo)識(shí)
數(shù)據(jù)手冊(cè)

下載地址一下載地址二到原廠下載

更新時(shí)間

2025-1-25 23:00:00

HS1-3182-8規(guī)格書(shū)詳情

The HS-3182 is a monolithic dielectric ally isolated bipolar

differential line driver designed to meet the specifications of

ARINC 429. This device is intended to be used with a

companion chip, HS-3282 CMOS ARINC Bus Interface

Circuit, which provides the data formatting and processor

interface function.

All logic inputs are TTL and CMOS compatible. In addition to

the DATA (A) and DATA (B) inputs, there are also inputs for

CLOCK and SYNC signals which are AND’d with the DATA

inputs. This feature enhances system performance and

allows the HS-3182 to be used with devices other than the

HS-3182.

Three power supplies are necessary to operate the HS-3182:

+V = +15V ±10, -V = -15V ±10, and V1 = 5V ±5. VREF is

used to program the differential output voltage swing such that

VOUT (DIFF) = ±2VREF. Typically, VREF = V1 = 5V ±5, but a

separate power supply may be used for VREF which should

not exceed 6V.

The driver output impedance is 75Ω ±20 at +25°C. Driver

output rise and fall times are independently programmed

through the use of two external capacitors connected to the CA

and CB inputs. Typical capacitor values are CA = CB = 75pF for

high-speed operation (100kBPS), and CA = CB = 300pF for

low-speed operation (12kBPS to 14.5kBPS). The outputs are

protected against overvoltage and short circuit as shown in the

Block Diagram. The HS-3182 is designed to operate over an

ambient temperature range of -55°C to +125°C, or -40°C to

+85°C

Features

? RoHS/Pb-free Available for SBDIP Package (100 Gold

Termination Finish)

? TTL and CMOS Compatible Inputs

? Adjustable Rise and Fall Times via Two External

Capacitors

? Programmable Output Differential Voltage via VREF Input

? Operates at Data Rates Up to 100k Bits/s

? Output Short Circuit Proof and Contains Overvoltage

Protection

? Outputs are Inhibited (0V) If DATA (A) and DATA (B)

Inputs are Both in the “Logic One” State

? DATA (A) and DATA (B) Signals are “AND’d” with Clock

and Sync Signals

? Full Military Temperature Range

產(chǎn)品屬性

  • 型號(hào):

    HS1-3182-8

  • 制造商:

    Intersil Corporation

  • 功能描述:

    LINE DRVR 16PIN SBCDIP - Rail/Tube

供應(yīng)商 型號(hào) 品牌 批號(hào) 封裝 庫(kù)存 備注 價(jià)格
INTERSIL
23+
NA/
15
優(yōu)勢(shì)代理渠道,原裝正品,可全系列訂貨開(kāi)增值稅票
詢價(jià)
LT
23+
ZIP
6500
全新原裝假一賠十
詢價(jià)
INTERSI
2020+
DIP
8000
只做自己庫(kù)存,全新原裝進(jìn)口正品假一賠百,可開(kāi)13%增
詢價(jià)
INTERSIL
24+
CDIP
13500
免費(fèi)送樣原盒原包現(xiàn)貨一手渠道聯(lián)系
詢價(jià)
INTERSIL,
22+23+
原廠原包
24052
絕對(duì)原裝正品現(xiàn)貨,全新深圳原裝進(jìn)口現(xiàn)貨
詢價(jià)
INTERSIL
22+
DIP-16
8000
原裝正品支持實(shí)單
詢價(jià)
INTERSIL
QQ咨詢
CDIP
839
全新原裝 研究所指定供貨商
詢價(jià)
HARRIS
24+
DIP
7
詢價(jià)
INTERSIL
24+
DIP16
16800
絕對(duì)原裝進(jìn)口現(xiàn)貨,假一賠十,價(jià)格優(yōu)勢(shì)!?
詢價(jià)
INTERSIL
19+
CDIP
2539
原廠代理渠道,每一顆芯片都可追溯原廠;
詢價(jià)