HSP50306SC-2596中文資料Intersil數(shù)據(jù)手冊PDF規(guī)格書

Description

The HSP50306 is a 6-bit QPSK demodulator chip designed for use in high signal to noise environments which have some multipath distortion. The part recovers 2.048 MBPS data from samples of a QPSK modulated 10.7MHz or 2.1MHz carrier. The chip coherently demodulates the waveform, recovers symbol timing, adaptively equalizes the signal to remove multipath distortion, differentially decodes and multiplexes the data decisions. 8-A lock signal is provided to indicate when the tracking loops are locked and the data decisions are valid. To optimize performance, a gain error feedback signal is provided which can be filtered and used to close an I.F. AGC loop around the A/D converter.

Features

? 25.6MHz or 26.97MHz Clock Rates

? Single Chip QPSK Demodulator with 10kHz Tracking Loop

? Square Root of Raised Cosine (α = 0.4) Matched Filtering

? 2.048 MBPS Reconstructed Output Data Stream

? Bit Synchronization with 3kHz Loop Bandwidth

? Internal Equalization for Multipath Distortion

? 6-Bit Real Input: Digitized 10.7MHz or 2.1MHz IF

? Level Detection for External IF AGC Loop

? 0.1s Acquisition Time

? 10-9 BER

?

Applications

? Cable Data Link Receivers

? Cable Control Channel Receivers