HSP9501JC-25中文資料Intersil數(shù)據(jù)手冊(cè)PDF規(guī)格書

The HSP9501 is a 10-Bit wide programmable data buffer designed for use in high speed digital systems. Two different modes of operation can be selected through the use of the MODSEL input. In the delay mode, a programmable data pipeline is created which can provide 2 to 1281 clock cycles of delay between the input and output data. In the data recirculate mode, the output data path is internally routed back to the input to provide a programmable circular buffer.

Features

? DC to 32MHz Operating Frequency

? Programmable Buffer Length from 2 to 1281 Words

? Supports Data Words to 10-Bits

? Clock Select Logic for Positive or Negative Edge System Clocks

? Data Recirculate or Delay Modes of Operation

? Expandable Data Word Width or Buffer Length

? Three-State Outputs

? TTL Compatible Inputs/Outputs

? Low Power CMOS

Applications

? Sample Rate Conversion

? Data Time Compression/Expansion

? Software Controlled Data Alignment

? Programmable Serial Data Shifting

? Audio/Speech Data Processing Video/Image Processing