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HY57V121620LT中文資料海力士數(shù)據(jù)手冊PDF規(guī)格書
HY57V121620LT規(guī)格書詳情
DESCRIPTION
The HY57V121620 is a 512-Mbit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY57V121620 is organized as 4banks of 8,388,608x16.
HY57V121620 is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL.
FEATURES
? Single 3.3±0.3V power supply
? All device pins are compatible with LVTTL interface
? JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin pitch
? All inputs and outputs referenced to positive edge of system clock
? Data mask function by UDQM, LDQM
? Internal four banks operation
? Auto refresh and self refresh
? 8192 refresh cycles / 64ms
? Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or Full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
? Programmable CAS Latency ; 2, 3 Clocks
產(chǎn)品屬性
- 型號：
HY57V121620LT
- 制造商：
HYNIX
- 制造商全稱：
Hynix Semiconductor
- 功能描述：
4 Banks x 8M x 16Bit Synchronous DRAM
| 供應(yīng)商 | 型號 | 品牌 | 批號 | 封裝 | 庫存 | 備注 | 價(jià)格 |
|---|---|---|---|---|---|---|---|
HYNIX |
24+ |
TSOP |
990000 |
明嘉萊只做原裝正品現(xiàn)貨 |
詢價(jià) | ||
HYNIX/海力士 |
24+ |
TSOP-54 |
68600 |
原裝現(xiàn)貨 |
詢價(jià) | ||
SKHYNIX |
09+ |
TSOP54 |
87 |
全新原裝只做自己庫存只做原裝 |
詢價(jià) | ||
Skhynix |
1844+ |
TSOP |
6528 |
只做原裝正品假一賠十為客戶做到零風(fēng)險(xiǎn)!! |
詢價(jià) | ||
HYNIX |
22+23+ |
TSOP |
21856 |
絕對原裝正品全新進(jìn)口深圳現(xiàn)貨 |
詢價(jià) | ||
HY |
SOP |
15620 |
一級代理 原裝正品假一罰十價(jià)格優(yōu)勢長期供貨 |
詢價(jià) | |||
HYNIX |
1011 |
15 |
公司優(yōu)勢庫存 熱賣中! |
詢價(jià) | |||
HY |
24+ |
TSSOP |
35200 |
一級代理/放心采購 |
詢價(jià) | ||
HYNIX |
19+ |
256800 |
原廠代理渠道,每一顆芯片都可追溯原廠； |
詢價(jià) | |||
HYNIX |
23+ |
TSOP |
8000 |
專注配單,只做原裝進(jìn)口現(xiàn)貨 |
詢價(jià) |
