HY57V651620B中文資料海力士數(shù)據(jù)手冊PDF規(guī)格書

DESCRIPTION

The Hynix HY57V641620HG is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY57V641620HG is organized as 4banks of 1,048,576 x 16.

FEATURES

? Single 3.3±0.3V power supplyNote)

? All device pins are compatible with LVTTL interface

? JEDEC standard 400mil 54 pin TSOP-II with 0.8mm of pin pitch

? All inputs and outputs referenced to positive edge of system clock

? Data mask function by UDQM or LDQM

? Internal four banks operation

? Auto refresh and self refresh

? 4096 refresh cycles/64ms

? Programmable Burst Length and Burst Type

-1, 2, 4, 8 or Full page for Sequential Burst

-1, 2, 4 or 8 for Interleave Burst

? Programmable CAS Latency; 2, 3 Clocks