HYB3164405J-60中文資料西門子數(shù)據(jù)手冊PDF規(guī)格書

16M x 4-Bit Dynamic RAM (4k & 8k Refresh, EDO-version)

This HYB3164(5)405 is a 64 MBit dynamic RAM organized 16 777 216 by 4 bits. The device is fabricated in SIEMENS/IBM most advanced first generation 64Mbit CMOS silicon gate process technology. The circuit and process design allow this device to achieve high performance and low power dissipation. The HYB3164(5)405 operates with a single 3.3 +/-0.3V power supply and interfaces with either LVTTL or LVCMOS levels. Multiplexed address inputs permit the HYB 3164(5)400J/T to be packaged in a 500mil wide SOJ-34 or TSOP-34 plastic package. These packages provide high system bit densities and are compatible with commonly used automatic testing and insertion equipment.The HYB3164(5)405TL parts have a very low power ?sleep mode“ supported by Self Refresh.

Preliminary Information

? 16 777 216 words by 4-bit organization

? 0 to 70 ?C operating temperature

? Fast access and cycle time

RAS access time:

50 ns (-50 version)

60 ns (-60 version)

Cycle time:

84 ns (-50 version)

104 ns (-60 version)

CAS access time:

13 ns ( -50 version)

15 ns ( -60 version)

? Hyper page mode (EDO) cycle time

20 ns (-50 version)

25 ns (-60 version)

? Single + 3.3 V (± 0.3V) power supply

? Low power dissipation

max. 396 active mW ( HYB 3164405J/T(L)-50)

max. 360 active mW ( HYB 3164405J/T(L)-60)

max. 504 active mW ( HYB 3165405J/T(L)-50)

max. 432 active mW ( HYB 3165405J/T(L)-60)

7.2 mW standby (TTL)

720 W standby (MOS)

14.4 mW Self Refresh (L-version only)

? Read, write, read-modify-write, CAS-before-RAS refresh (CBR), RAS-only refresh, hidden refresh and self refresh modes

? Hyper page mode (EDO) capability

? 8192 refresh cycles/128 ms , 13 R/ 11C addresses (HYB 3164405J/T(L))

? 4096 refresh cycles/ 64 ms , 12 R/ 12C addresses (HYB 3165405J/T(L))

? Plastic Package:

P-SOJ-34-1 500 mil HYB 3164(5)400J

P-TSOPII-34-1 500 mil HYB 3164(5)400T