HYB3165160T-50中文資料西門子數(shù)據(jù)手冊(cè)PDF規(guī)格書

4M x 16-Bit Dynamic RAM (4k & 8k Refresh)

This device is a 64 MBit dynamic RAM organized 4 194 304 by 16 bits. The device is fabricated in SIEMENS/IBM most advanced first generation 64Mbit CMOS silicon gate process technology. The circuit and process design allow this device to achieve high performance and low power dissipation. This DRAM operates with a single 3.3 +/-0.3V power supply and interfaces with either LVTTL or LVCMOS levels. Multiplexed address inputs permit the HYB 3164(5)160T to be packaged in a 500 mil wide TSOP-54 plastic package. These packages provide high system bit densities and are compatible with commonly used automatic testing and insertion equipment.

Preliminary Information

? 4 194 304 words by 16-bit organization

? 0 to 70 ?C operating temperature

? Fast access and cycle time

RAS access time:

50 ns (-50 version)

60 ns (-60 version)

Cycle time:

90 ns (-50 version)

110 ns (-60 version)

CAS access time:

13 ns ( -50 version)

15 ns ( -60 version)

? Fast page mode cycle time

35 ns (-50 version)

40 ns (-60 version)

? Single + 3.3 V (± 0.3V) power supply

? Low power dissipation

max. 396 active mW ( HYB 3164160T-50)

max. 360 active mW ( HYB 3164160T-60)

max. 504 active mW ( HYB 3165160T-50)

max. 432 active mW ( HYB 3165160T-60)

7.2 mW standby (TTL)

720 W standby (MOS)

? Read, write, read-modify-write, CAS-before-RAS refresh (CBR), RAS-only refresh, hidden refresh and self refresh modes

? Fast page mode capability

? 2 CAS / 1 WRITE byte control

? 8192 refresh cycles/128 ms , 13 R/ 9C addresses (HYB 3164160T)

? 4096 refresh cycles/ 64 ms , 12 R/ 10C addresses (HYB 3165160T)

? Plastic Package: P-TSOPII-54-1 500 mil