HYM362140S-60中文資料西門子數(shù)據(jù)手冊PDF規(guī)格書

The HYM 362140S/GS-60/-70 is a 8 M Byte DRAM module organized as 2 097 152 words by 36-bit in a 72-pin single-in-line package comprising eight HYB 511000BJ 1M × 1 DRAMs and sixteen HYB 514400BJ 1M × 4 DRAMs in 300 mil wide SOJ-packages mounted together with twelve 0.2 μF ceramic decoupling capacitors on a PC board.

Advanced Information

? 2 097 152 words by 36-bit organization (alternative 4 194 304 words by 18-bit)

? Fast access and cycle time

60 ns access time

110 ns cycle time (-60 version)

70 ns access time

130 ns cycle time (-70 version)

? Fast page mode capability with

40 ns cycle time (-60 version)

45 ns cycle time (-70 version)

? Single + 5 V (± 10 ) supply

? Low power dissipation

max. 6952 mW active (-60 version)

max. 6292 mW active (-70 version)

CMOS – 132 mW standby

TTL – 264 mW standby

? CAS-before-RAS refresh

RAS-only-refresh

Hidden-refresh

? 12 decoupling capacitors mounted on substrate

? All inputs, outputs and clocks fully TTL compatible

? 72 pin Single in-Line Memory Module with 31.75 mm height

? Utilizes eight 1M × 1-DRAMs and sixteen 1M × 4 DRAMs in 300 mil SOJ-packages

? 1024 refresh cycles / 16 ms

? Tin-Lead contact pads (S - version)

? God contact pads (GS - version)