I74F112N中文資料飛利浦?jǐn)?shù)據(jù)手冊(cè)PDF規(guī)格書
I74F112N規(guī)格書詳情
DESCRIPTION
The 74F112, Dual Negative Edge-Triggered JK-Type Flip-Flop, feature individual J, K, Clock (CPn), Set (SD) and Reset (RD) inputs, true (Qn) and complementary (Qn) outputs.
The SD and RD inputs, when Low, set or reset the outputs as shown in the Function Table, regardless of the level at the other inputs.
A High level on the clock (CPn) input enables the J and K inputs and data will be accepted. The logic levels at the J and K inputs may be allowed to change while the CPn is High and flip-flop will perform according to the Function Table as long as minimum setup and hold times are observed. Output changes are initiated by the High-to-Low transition of the CPn.
FEATURE
? Industrial temperature range available (–40°C to +85°C)
產(chǎn)品屬性
- 型號(hào)：
I74F112N
- 制造商：
NXP Semiconductors
- 功能描述：
Flip Flop JK-Type Neg-Edge 2-Element 16-Pin PDIP
| 供應(yīng)商 | 型號(hào) | 品牌 | 批號(hào) | 封裝 | 庫存 | 備注 | 價(jià)格 |
|---|---|---|---|---|---|---|---|
NXP/恩智浦 |
23+ |
NA/ |
3390 |
原裝現(xiàn)貨,當(dāng)天可交貨,原型號(hào)開票 |
詢價(jià) | ||
PHILIPS |
24+ |
35200 |
一級(jí)代理/放心采購 |
詢價(jià) | |||
PHILIPS |
23+ |
NA |
6486 |
專做原裝正品,假一罰百! |
詢價(jià) | ||
NXP大量供貨 |
SOP |
68900 |
原包原標(biāo)簽100%進(jìn)口原裝常備現(xiàn)貨! |
詢價(jià) | |||
NXP |
21+ |
16SOIC |
13880 |
公司只售原裝,支持實(shí)單 |
詢價(jià) | ||
PHILIPS |
23+ |
SOP-14 |
5500 |
現(xiàn)貨,全新原裝 |
詢價(jià) | ||
NXP |
22+ |
SOP |
9852 |
只做原裝正品現(xiàn)貨!或訂貨假一賠十! |
詢價(jià) | ||
NXP USA Inc. |
23+ |
7300 |
專注配單,只做原裝進(jìn)口現(xiàn)貨 |
詢價(jià) | |||
NXP |
2022+ |
原廠原包裝 |
8600 |
全新原裝 支持表配單 中國(guó)著名電子元器件獨(dú)立分銷 |
詢價(jià) | ||
NXP |
23+ |
S016 |
8000 |
只做原裝現(xiàn)貨 |
詢價(jià) |
