I74F112N中文資料飛利浦?jǐn)?shù)據(jù)手冊(cè)PDF規(guī)格書
| 廠商型號(hào) |
I74F112N |
| 功能描述 | Dual J-K negative edge-triggered flip-flop |
| 文件大小 |
83.94 Kbytes |
| 頁(yè)面數(shù)量 |
10 頁(yè) |
| 生產(chǎn)廠商 | NXP Semiconductors |
| 企業(yè)簡(jiǎn)稱 |
Philips【飛利浦】 |
| 中文名稱 | 荷蘭皇家飛利浦官網(wǎng) |
| 原廠標(biāo)識(shí) |  |
| 數(shù)據(jù)手冊(cè) | |
| 更新時(shí)間 | 2025-3-26 11:34:00 |
| 人工找貨 | I74F112N價(jià)格和庫(kù)存，歡迎聯(lián)系客服免費(fèi)人工找貨 |
I74F112N規(guī)格書詳情
DESCRIPTION
The 74F112, Dual Negative Edge-Triggered JK-Type Flip-Flop, feature individual J, K, Clock (CPn), Set (SD) and Reset (RD) inputs, true (Qn) and complementary (Qn) outputs.
The SD and RD inputs, when Low, set or reset the outputs as shown in the Function Table, regardless of the level at the other inputs.
A High level on the clock (CPn) input enables the J and K inputs and data will be accepted. The logic levels at the J and K inputs may be allowed to change while the CPn is High and flip-flop will perform according to the Function Table as long as minimum setup and hold times are observed. Output changes are initiated by the High-to-Low transition of the CPn.
FEATURE
? Industrial temperature range available (–40°C to +85°C)
產(chǎn)品屬性
- 型號(hào)：
I74F112N
- 制造商：
NXP Semiconductors
- 功能描述：
Flip Flop JK-Type Neg-Edge 2-Element 16-Pin PDIP
| 供應(yīng)商 | 型號(hào) | 品牌 | 批號(hào) | 封裝 | 庫(kù)存 | 備注 | 價(jià)格 |
|---|---|---|---|---|---|---|---|
PHILIPS |
23+ |
SOP-14 |
5500 |
現(xiàn)貨,全新原裝 |
詢價(jià) | ||
NXP/恩智浦 |
23+ |
SOP16 |
4000 |
一級(jí)代理原廠VIP渠道,專注軍工、汽車、醫(yī)療、工業(yè)、 |
詢價(jià) | ||
NXP |
23+ |
S016 |
8000 |
只做原裝現(xiàn)貨 |
詢價(jià) | ||
PHILIPS |
1922+ |
SOP14-3.9MM |
12600 |
詢價(jià) | |||
NXP/恩智浦 |
23+ |
SOP |
50000 |
全新原裝正品現(xiàn)貨,支持訂貨 |
詢價(jià) | ||
NXP/恩智浦 |
1948+ |
SOP14 |
6852 |
只做原裝正品現(xiàn)貨!或訂貨假一賠十! |
詢價(jià) | ||
NXP |
22+ |
16SOIC |
9000 |
原廠渠道,現(xiàn)貨配單 |
詢價(jià) | ||
NXP |
21+ |
16SOIC |
13880 |
公司只售原裝,支持實(shí)單 |
詢價(jià) | ||
PHILIPS |
24+ |
35200 |
一級(jí)代理/放心采購(gòu) |
詢價(jià) | |||
NXP大量供貨 |
21+ |
SOP |
10000 |
原裝現(xiàn)貨假一罰十 |
詢價(jià) |
