IC42S16102-7BIG中文資料ICSI數(shù)據(jù)手冊PDF規(guī)格書

DESCRIPTION

ICSIs 16Mb Synchronous DRAM IC42S16102 is organized as a 524,288-word x 16-bit x 2-bank for improved performance. The synchronous DRAMs achieve high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input.

FEATURES

? Driver Strength for High capacitive bus loading

? Clock frequency: 200, 166, 143 MHz

? Fully synchronous; all signals referenced to a positive clock edge

? Two banks can be operated simultaneously and independently

? Dual internal bank controlled by A11 (bank select)

? Single 3.3V power supply

? LVTTL interface

? Programmable burst length – (1, 2, 4, 8, full page)

? Programmable burst sequence: Sequential/Interleave

? Auto refresh, self refresh

? 4096 refresh cycles every 64 ms

? Random column address every clock cycle

? Programmable CAS latency (2, 3 clocks)

? Burst read/write and burst read/single write operations capability

? Burst termination by burst stop and precharge command

? Byte controlled by LDQM and UDQM

? Package 400mil 50-pin TSOP-2 and 60ball(16M) VF-BGA

? Pb(lead)-free package is available