IC42S32200/L-6T中文資料ICST數(shù)據(jù)手冊(cè)PDF規(guī)格書

DESCRIPTION

The ICSI IC42S32200 and IC42S32200L is a high-speed CMOS configured as a quad 512K x 32 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal,CLK).

Each of the 512K x 32 bit banks is organized as 2048 rows by 256 columns by 32 bits.Read and write accesses start at a selected locations in a programmed sequence. Accesses begin with the registration of a BankActive command which is then followed by a Read or Write command

FEATURES

? Concurrent auto precharge

? Clock rate:166/143/125 MHz

? Fully synchronous operation

? Internal pipelined architecture

? Four internal banks (512K x 32bit x 4bank)

? Programmable Mode

-CAS#Latency:2 or 3

-Burst Length:1,2,4,8,or full page

-Burst Type:interleaved or linear burst

-Burst-Read-Single-Write

? Burst stop function

? Individual byte controlled by DQM0-3

? Auto Refresh and Self Refresh

? 4096 refresh cycles/64ms

? Single +3.3V ±0.3V power supply

? Interface:LVTTL

? Package:400 x 875 mil,86 Pin TSOP-2,0.50mm Pin Pitch and 11x13mm, 90 Ball BGA, Ball pitch 0.8mm

? Pb-free package is available.