ICS672-01中文資料華潤(rùn)微電子數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

Description

The ICS672-01 and ICS672-02 are zero delay buffers that generate four output clocks whose phases are spaced at 90° intervals. Based on ICS’ proprietary low jitter Phase Locked Loop (PLL) techniques, each device provides five low skew outputs, with clock rates up to 84 MHz for the ICS672-01 and up to 135 MHz for the ICS672-02. By providing outputs delayed one quarter clock cycle, the device is useful for systems requiring early or late clocks.

Features

? Packaged in 16 pin narrow SOIC

? Input clock range from 10 MHz to 150 MHz

? Clock outputs from up to 84 MHz (ICS672-01)

and up to 135 MHz (ICS672-02)

? Zero input-output delay

? Integrated x0.5, x1, x2, x3, x4, x5, or x6 selections

? Four accurate (<250 ps) outputs with 0°, 90°,

180°, and 270° phase shift from ICLK, and one

FBCLK (0°)

? Separate supply for output clocks from 2.5V to 5V

? Full CMOS outputs (TTL compatible)

? Tri state mode for board-level testing

? Includes Power Down for power savings

? Advanced, low power, sub-micron CMOS process

? 3.3 V to 5 V operating voltage

? Industrial temperature version available