ICS8432-101中文資料瑞薩數(shù)據(jù)手冊PDF規(guī)格書

FEATURES

? Dual differential 3.3V LVPECL outputs

? Selectable CLK, nCLK or LVCMOS/LVTTL TEST_CLK

? TEST_CLK can accept the following input levels:

LVCMOS or LVTTL

? CLK, nCLK pair can accept the following differential

input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL

? CLK, nCLK or TEST_CLK maximum input frequency: 40MHz

? Output frequency range: 25MHz to 700MHz

? VCO range: 250MHz to 700MHz

? Accepts any single-ended input signal on CLK input with

resistor bias on nCLK input

? Parallel interface for programming counter and output dividers

? RMS period jitter: 5ps (maximum)

? Cycle-to-cycle jitter: 25ps (maximum)

? 3.3V supply voltage

? 0°C to 70°C ambient operating temperature

? Available in both standard (RoHS 5) and lead-free (RoHS 6) packages