ICS8530-01中文資料瑞薩數(shù)據(jù)手冊PDF規(guī)格書

Features

? Sixteen differential 3.3V LVPECL outputs

? CLK, nCLK input pair

? CLK, nCLK pair can accept the following differential input

levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL

? Maximum output frequency: 500MHz

? Translates any single-ended input signal to 3.3V LVPECL levels

with a resistor bias on nCLK input

? Output skew: 75ps (maximum)

? Part-to-part skew: 305ps (maximum)

? Additive phase jitter, RMS: 0.03ps (typical)

? Full 3.3V supply voltage

? 0°C to 70°C ambient operating temperature

? Available in both standard (RoHS 5) and lead-free (RoHS 6)

packages