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ICS854054AGT中文資料華潤(rùn)微電子數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

ICS854054AGT
廠商型號(hào)

ICS854054AGT

功能描述

DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER

文件大小

250.68 Kbytes

頁(yè)面數(shù)量

13 頁(yè)

生產(chǎn)廠商 China Resources Microelectronics Limited Limited
企業(yè)簡(jiǎn)稱(chēng)

ICST華潤(rùn)微電子

中文名稱(chēng)

華潤(rùn)微電子有限公司官網(wǎng)

原廠標(biāo)識(shí)
數(shù)據(jù)手冊(cè)

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更新時(shí)間

2024-11-19 18:36:00

ICS854054AGT規(guī)格書(shū)詳情

GENERAL DESCRIPTION

The ICS854054 is a 4:1 Differential-to-LVDS Clock Multiplexer which can operate up to 2.8GHz and is a member of the HiPerClockS? family of High Performance Clock Solutions from ICS. The ICS854054 has 4 selectable differential clock inputs. The PCLK, nPCLK input pairs can accept LVPECL, LVDS, CML or SSTL levels. The fully differential architecture and low propagation delay make it ideal for use in clock distribution circuits. The select pins have internal pulldown resistors. The SEL1 pin is the most significant bit and the binary number applied to the select pins will select the same numbered data input (i.e., 00 selects PCLK0, nPCLK0).

FEATURES

? High speed 4:1 differential multiplexer

? One differential LVDS output

? Four selectable differential clock inputs

? PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL

? Maximum output frequency: 2.8GHz

? Translates any single ended input signal to LVDS levels with resistor bias on nPCLKx input

? Part-to-part skew: 375ps (maximum)

? Propagation delay: 700ps (maximum)

? Supply voltage range: 3.135V to 3.465V

? -40°C to 85°C ambient operating temperature

? Available in both standard and lead-free RoHS compliant packages

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IDT
1815+
TSSOP24
6528
只做原裝正品假一賠十為客戶(hù)做到零風(fēng)險(xiǎn)!!
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IDT
2017+
SSOP24
18700
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IDT
23+
20-TSSOP
7750
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ICSI
2022
TSSOP-24
80000
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ICS
21+
TSSOP-24
10000
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ICS
TSSOP-24
68900
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IDT
2023+
SSOP24
6893
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ICS854058AG
3
3
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IDT
標(biāo)準(zhǔn)封裝
57598
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21+
20TSSOP
13880
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