ICS9147-03中文資料ICST數(shù)據(jù)手冊PDF規(guī)格書

General Description

The ICS9147-03 generates all clocks required for high speed RISC or CISC microprocessor systems such as Intel PentiumPro, AMD or Cyrix processors. Four bidirectional I/O pins (FS0, FS1, FS2, BSEL) are latched at power-on to the functionality table. The Six BUS clocks can be selected as either synchronous at 1/2 CPU speed or asynchronous at 32MHz selected by BSEL latched input.The inputs provide for tristate and test mode conditions to aid in system level testing.These multiplying factors can be customized for specific applications. Glitch-free stop clock controls provided for SDRAM(5:8) and SDRAM (9:12) banks (STP2#, STP3#).

Features

? Total of 15 CPU speed clocks:

- Two copies of CPU clock with VDDL (2.5 to 3.3V)

- Twelve (12) SDRAM (3.3v) plus one CPUH/AGP (3.3V) clocks

? Six copies of BUS clocks (synchronous with CPU clock/2 or asynchronous 32 MHz)

? 250ps output skew window for CPU andSDRAM clocks and 500ps window BUS clocks. CPU clocks to BUS clocks skew 1-4ns (CPU early)

? Two copies of Ref. clock @14.31818 MHz (One driven by VDDL as IOAPIC)

? One 48 MHz (3.3 V TTL) for USB support and single 24 MHz.

? Separate VDDL for CPUL (1:2) clock buffers and IOAPIC to allow 2.5V output (or Std. Vdd)

? 3.0V – 3.7V supply range w/2.5V compatible outputs

? 48-pin SSOP package