IDT2305B集成電路（IC）的時鐘發(fā)生器PLL頻率合成器規(guī)格書PDF中文資料

DESCRIPTION:

The IDT2305B is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz.

FEATURES:

? Phase-Lock Loop Clock Distribution

? 10MHz to 133MHz operating frequency

? Distributes one clock input to one bank of five outputs

? Zero Input-Output Delay

? Output Skew < 250ps

? Low jitter <200 ps cycle-to-cycle

? IDT2305B-1 for Standard Drive

? IDT2305B-1H for High Drive

? No external RC network required

? Operates at 3.3V VDD

? Power down mode

? Available in SOIC package