IDT2309B-1DCGBLANK中文資料IDT數(shù)據(jù)手冊PDF規(guī)格書

DESCRIPTION:

The IDT2309B is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz.

FEATURES:

? Phase-Lock Loop Clock Distribution

? 10MHz to 133MHz operating frequency

? Distributes one clock input to one bank of five and one bank of four outputs

? Separate output enable for each output bank

? Output Skew < 250ps

? Low jitter <175 ps cycle-to-cycle

? 50ps typical cycle-to-cycle jitter (15pF, 66MHz)

? IDT2309B-1 for Standard Drive

? IDT2309B-1H for High Drive

? No external RC network required

? Operates at 3.3V VDD

? Available in SOIC and TSSOP packages

APPLICATIONS:

? SDRAM

? Telecom

? Datacom

? PC Motherboards/Workstations

? Critical Path Delay Designs