IDT29FCT520AT中文資料IDT數(shù)據(jù)手冊PDF規(guī)格書

DESCRIPTION:

The IDT29FCT520AT/BT/CT/DT and IDT29FCT521AT/BT/CT/DT each contain four 8-bit positive edge-triggered registers. These may be operated as a dual 2-level or as a single 4-level pipeline. A single 8-bit input is provided and any of the four registers is available at the 8-bit, 3-state output.

These devices differ only in the way data is loaded into and between the registers in 2-level operation. The difference is illustrated in Figure 1. In the IDT29FCT520AT/BT/CT/DT when data is entered into the first level (I = 2 or I = 1), the existing data in the first level is moved to the second level. In the IDT29FCT521AT/BT/CT/DT, these instructions simply cause the data in the first level to be overwritten. Transfer of data to the second level is achieved using the 4-level shift instruction (I = 0). This transfer also causes the first level to change. In either part I=3 is for hold.

FEATURES:

? A, B, C and D speed grades

? Low input and output leakage ≤1μA (max.)

? CMOS power levels

? True TTL input and output compatibility

– VOH = 3.3V (typ.)

– VOL = 0.3V (typ.)

? High drive outputs (-15mA IOH, 48mA IOL)

? Meets or exceeds JEDEC standard 18 specifications

? Product available in Radiation Tolerant and Radiation Enhanced versions

? Military product compliant to MIL-STD-883, Class B and DESC listed (dual marked)

? Available in DIP, SOIC, SSOP, QSOP, CERPACK and LCC packages