IDT54FCT138SO中文資料IDT數(shù)據(jù)手冊(cè)PDF規(guī)格書

DESCRIPTION:

The IDT54/74FCT138/A/C are 1-of-8 decoders built using an advanced dual metal CMOS technology. The IDT54/74FCT138/A/C accept three binary weighted inputs (A0, A1, A2) and, when enabled, provide eight mutually exclusive active LOW outputs (O0- O7). The IDT54/74FCT138/A/C feature three enable inputs, two active LOW (E1, E2) and one active HIGH (E3). All outputs will be HIGH unless E1and E2 are LOW and E3is HIGH. This multiple enable function allows easy parallel expansion of the device to a 1-of-32 (5 lines to

32 lines) decoder with just four IDT54/74FCT138/A/C devices and one inverter.

FEATURES:

? IDT54/74FCT138 equivalent to FAST?speed

? IDT54/74FCT138A 35 faster than FAST

? IDT54/74FCT138C 40 faster than FAST

? Equivalent to FAST speeds output drive over full temperature and voltage supply extremes

? IOL= 48mA (commercial) and 32mA (military)

? CMOS power levels (1mW typ. static)

? TTL input and output level compatible

? CMOS output level compatible

? Substantially lower input current levels than FAST (5μA max.)

? JEDEC standard pinout for DIP and LCC

? Product available in Radiation Tolerant and Radiation Enhanced versions

? Military product compliant to MIL-STD-883, Class B

? Standard Military Drawing # 5962-87654 is listed on this function. Refer to section 2.